View A6276_8159050.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

description the A6276 is specifically designed for led-display applications. each bicmos device includes a 16-bit cmos shift register, accompanying data latches, and 16 npn constant- current sink drivers. except for package style and allowable package power dissipation, the device options are identical. the cmos shift register and latches allow direct interfacing with microprocessor-based systems. with a 5 v logic supply, typical serial data-input rates are up to 20 mhz. the led drive current is de ter mined by the user selection of a single resistor. a cmos serial data output permits cascaded connections in applications requiring additional drive lines. for inter-digit blanking, all output drivers can be disabled with an enable input high. similar 8-bit devices are available as the a6275. three package styles are provided: through-hole dip (suffix a), surface-mount soic (suffix lw), and tssop with exposed thermal pad (suffix lp). in normal applications, the copper leadframe and low logic-power dissipation of the dip allow it to sink maximum rated current through all outputs con tin u ous ly over the operating temperature range (90 ma, 0.75 v drop, 85c). all packages are lead (pb) free, with 100% matte tin leadframe plating. 26185.201h features and benefits ? up to 90 ma constant-current outputs ? undervoltage lockout ? low-power cmos logic and latches ? high data input rate ? functional replacement for tb62706bn/bf 16-bit serial input, constant-current latched led driver functional block diagram A6276 packages not to scale 24-pin dip (a package) 24-pin soicw (lw package) 24-pin tssop with exposed thermal pad (lp package)
16-bit serial input, constant-current latched led driver A6276 2 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com selection guide part number package packing ambient temperature (c) A6276ea-t 24-pin dip 15 per tube ?40 to 85 A6276elptr-t * 24-pin tssop 4000 per reel ?40 to 85 A6276elwtr-t 24-pin soicw 1000 per reel ?40 to 85 A6276slwtr-t * 24-pin soicw 1000 per reel ?20 to 85 * variant is in production but has been determined to be last time buy. this classification indicates that the variant is obsolete and notice has been given. sale of the variant is currently restricted to existing customer applications. the variant should not be purchased for new design applications because of obsolescence in the near future. samples are no longer available. status date change november 1, 2008. deadline for receipt of last time buy orders is april 25, 2009. absolute maximum ratings* characteristic symbol notes rating units supply voltage v dd 7.0 v output voltage v o ?0.5 to 17 v input voltage v rout ?0.4 to v dd + 0.4 v output current i o 90 ma ground current i gnd 1475 ma operating ambient temperature t a range s ?20 to 85 oc range e ?40 to 85 oc maximum junction temperature t j (max) 150 oc storage temperature t stg ?55 to 150 oc *caution: these cmos devices have input static protection (class 2) but are still sus cep ti ble to damage if exposed to extremely high static electrical charges. thermal characteristics may require derating at maximum conditions, see application information characteristic symbol test conditions* value units package thermal resistance r ja package a, 1-layer pcb based on jedec standard 50 oc/w package lp, 2-layer pcb with 3.8 in. 2 copper area each side 32 oc/w package lw, 1-layer pcb based on jedec standard 85 oc/w *additional thermal information available on the allegro website 2.5 0.5 2.0 3.5 3.0 4.0 1.5 1.0 0 50 75 100 125 150 allowable package power dissipation in watts ambient temperature in c 25 24-pin dip, r ja = 50c/w 24-pin tssop*, r ja = 32c/w 24-lead soic, r ja = 85c/w *mounted on single-layer, two-sided pcb, with 3.8 in 2 copper each side; additional information on allegro web site
16-bit serial input, constant-current latched led driver A6276 3 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ? 2000, 2003 allegro microsystems, inc. terminal description terminal no. terminal name function 1 gnd reference terminal for control logic. 2 serial data in serial-data input to the shift-register. 3 clock clock input terminal for data shift on rising edge. 4 latch enable data strobe input terminal; serial data is latched with high-level input. 5-20 out 0-15 the 16 current-sinking output ter mi nals. 21 output enable when (active) low, the output drivers are enabled; when high, all output drivers are turned off (blanked). 22 serial data out cmos serial-data output to the following shift-register. 23 r ext an external resistor at this terminal establishes the output current for all sink drivers. 24 supply (v dd ) the logic supply voltage (typically 5 v). ground register latches 1 2 3 18 19 20 21 23 4 5 6 7 22 24 serial data out logic supply serial data in output enable latch enable clock ck v dd oe out 1 out 2 out 0 out 12 out 14 out 13 out 3 out 15 r ext i regulator l o 12 9 10 11 out 5 out 6 out 4 out 7 13 14 15 16 8 17 out 8 out 10 out 9 out 11 pin-out diagram (a, lp, and lw packages)
16-bit serial input, constant-current latched led driver A6276 4 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com clock and serial data in serial data out latch enable output enable (active low) dwg. ep-010-11 in v dd dwg. ep-010-12 in v dd dwg. ep-010-13 in v dd truth table serial shift register contents serial latch latch contents output output con tents data clock data enable enable input input i 1 i 2 i 3 ... i n-1 i n output input i 1 i 2 i 3 ... i n-1 i n input i 1 i 2 i 3 ... i n-1 i n h h r 1 r 2 ... r n-2 r n-1 r n-1 l l r 1 r 2 ... r n-2 r n-1 r n-1 x r 1 r 2 r 3 ... r n-1 r n r n x x x ... x x x l r 1 r 2 r 3 ... r n-1 r n p 1 p 2 p 3 ... p n-1 p n p n h p 1 p 2 p 3 ... p n-1 p n l p 1 p 2 p 3 ... p n-1 p n x x x ... x x h h h h ... h h l = low logic (voltage) level h = high logic (voltage) level x = irrelevant p = present state r = previous state v dd dwg. ep-063-6 out
16-bit serial input, constant-current latched led driver A6276 5 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com electrical characteristics at t a = +25c, v dd = 5 v (unless otherwise noted). limits characteristic symbol test conditions min. typ. max. unit supply voltage range v dd operating 4.5 5.0 5.5 v under-voltage lockout v dd(uv) v dd = 0 5 v 3.4 ? 4.0 v output current i o v ce = 0.7 v, r ext = 250 ? 64.2 75.5 86.8 ma (any single output) v ce = 0.7 v, r ext = 470 ? 34.1 40.0 45.9 ma output current matching ? i o 0.4 v v ce(a) = v ce(b) 0.7 v: (difference between any r ext = 250 ? ? 1.5 6.0 % two outputs at same v ce ) r ext = 470 ? ? 1.5 6.0 % output leakage current i cex v oh = 15 v ? 1.0 5.0 a logic input voltage v ih 0.7v dd ? v dd v v il gnd ? 0.3v dd v serial data out v ol i ol = 500 a ? ? 0.4 v voltage v oh i oh = -500 a 4.6 ? ? v input resistance r i enable input, pull up 150 300 600 k ? latch input, pull down 100 200 400 k ? supply current i dd(off) r ext = open, v oe = 5 v ? 0.8 1.4 ma r ext = 470 , v oe = 5 v 3.5 6.0 8.0 ma r ext = 250 , v oe = 5 v 6.5 11 15 ma i dd(on) r ext = 470 ? , v oe = 0 v 7.0 13 20 ma r ext = 250 ? , v oe = 0 v 10 22 32 ma typical data is at v dd = 5 v and is for design information only.
16-bit serial input, constant-current latched led driver A6276 6 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com switching characteristics at t a = 25c, v dd = v ih = 5 v, v ce = 0.4 v, v il = 0 v, r ext = 470 , i o = 40 ma, v l = 3 v, r l = 65 , c l = 10.5 pf. limits characteristic symbol test conditions min. typ. max. unit propagation delay time t phl clock-out n ? 350 1000 ns latch-out n ? 350 1000 ns enable-out n ? 350 1000 ns clock-serial data out ? 40 ? ns propagation delay time t plh clock-out n ? 300 1000 ns latch-out n ? 300 1000 ns enable-out n ? 300 1000 ns clock-serial data out ? 40 ? ns output fall time t f 90% to 10% voltage 150 350 1000 ns output rise time t r 10% to 90% voltage 150 300 600 ns recommended operating conditions characteristic symbol conditions min. typ. max. unit supply voltage v dd 4.5 5.0 5.5 v output voltage v o ? 1.0 4.0 v output current i o continuous, any one output ? ? 90 ma i oh serial data out ? ? -1.0 ma i ol serial data out ? ? 1.0 ma logic input voltage v ih 0.7v dd ? v dd + 0.3 v v il -0.3 ? 0.3v dd v clock frequency f ck cascade operation ? ? 10 mhz
16-bit serial input, constant-current latched led driver A6276 7 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com timing requirements and specifications (logic levels are v dd and ground) serial data present at the input is transferred to the shift register on the logic 0-to-logic 1 transition of the clock input pulse. on succeeding clock pulses, the registers shift data in- formation towards the serial data output. the serial data must appear at the input prior to the rising edge of the clock input waveform. information present at any register is transferred to the respective latch when the latch enable is high (serial-to- par al lel con ver sion). the latches continue to accept new data as long as the latch enable is held high. ap pli ca tions where the latches are bypassed (latch enable tied high) will require that the output en able input be high during serial data entry. when the output enable input is high, the output sink driv ers are disabled (off). the in for ma tion stored in the latches is not affected by the output enable input. with the out- put enable input low, the outputs are con trolled by the state of their re spec tive latches. a. data active time before clock pulse (data set-up time), t su(d) ............................. 50 ns b. data active time after clock pulse (data hold time), t h(d) ................................. 20 ns c. clock pulse width, t w(ck) .................................. 50 ns d. time between clock ac ti va tion and latch enable, t su(l) ............................... 100 ns e. latch enable pulse width, t w(l) ...................... 100 ns f. output enable pulse width, t w(oe) ................... 4.5 s note: timing is representative of a 10 mhz clock. sig- nif i cant ly higher speeds are attainable. max. clock transition time, t r or t f ....................... 10 s clock serial data in latch enable output enable out n dwg. wp-029-1 50% serial data out data data 50% 50% 50% c a b d e low = all outputs enabled p t data 50% p t low = output on high = output off output enable out n dwg. wp-030-1a data 10% 50% phl t plh t high = all outputs disabled (blanked) f t r t 90% f 50%
16-bit serial input, constant-current latched led driver A6276 8 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com allowable output current as a function of duty cycle w l e 6 7 2 6 a a e 6 7 2 6 a 0 20 duty cycle in per cent 100 0 dwg. gp-062-11 allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v v ce = 3 v v ce = 4 v 80 t a = +25 o c v dd = 5 v r q ja = 50 o c/w 0 20 duty cycle in per cent 100 0 dwg. gp-062-10 allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v t a = +50 o c v dd = 5 v r q ja = 50 o c/w v ce = 3 v v ce = 4 v 80 0 20 duty cycle in per cent 100 0 dwg. gp-062-6 allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v v ce = 3 v 80 v ce = 4 v t a = +25 o c v dd = 5 v r q ja = 75 o c/w v ce = 0.7 v 0 20 duty cycle in per cent 100 0 dwg. gp-062-7 allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v v ce = 3 v 80 t a = +50 o c v dd = 5 v r q ja = 75 o c/w v ce = 0.7 v v ce = 4 v
16-bit serial input, constant-current latched led driver A6276 9 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 0 20 duty cycle in per cent 100 0 dwg. gp-062-9 allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v t a = +85 o c v dd = 5 v r q ja = 50 o c/w v ce = 3 v v ce = 0.7 v v ce = 4 v 80 allowable output current as a function of duty cycle (cont.) w l e 6 7 2 6 a a e 6 7 2 6 a typical characteristics 0.5 dwg. gp-063 1.0 2.0 1.5 v ce in volts 0 60 40 output current in ma/bit 20 0 t a = +25 o c r ext = 500 7 0 20 duty cycle in per cent 100 0 dwg. gp-062-8 allowable output current in ma/bit 60 40 20 40 60 100 80 v ce = 1 v v ce = 2 v v ce = 3 v 80 t a = +85 o c v dd = 5 v r q ja = 75 o c/w v ce = 4 v v ce = 0.7 v v ce = 0.4 v
16-bit serial input, constant-current latched led driver A6276 10 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com allowable output current as a func tion of duty cycle (cont.) A6276elp 0 20 duty cycle in per cent 100 0 allowable output current in ma/bit 60 40 20 40 60 100 80 v ce =1v v ce =2v v ce =3v v ce =4v 80 t a =+25 c v dd =5v r ? q ja =40 c/w 0 20 duty cycle in per cent 100 0 allowable output current in ma/bit 60 40 20 40 60 100 80 v ce =1v v ce =2v t a =+50 c v dd =5v r ? q ja =40 c/w v ce =3v v ce =4v 80
16-bit serial input, constant-current latched led driver A6276 11 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the load current per bit (i o ) is set by the external re sis tor (r ext ) as shown in the figure below. 300 500 700 1 k 2 k current-control resistance, r ext in ohms 100 0 100 dwg. gp-061 5 k 200 3 k 20 40 60 80 v ce = 0.7 v package power dissipation (p d ). the maximum al- low able package power dissipation is determined as p d (max) = (150 - t a )/r ? ja . the actual package power dissipation is p d (act) = dc ? (v ce ? i o ? 16) + (v dd ? i dd ) , where dc is the duty cycle. when the load supply voltage is greater than 3 v to 5 v, considering the package power dissipating limits of these devices, or if p d (act) > p d (max), an external voltage re- ducer (v drop ) should be used. load supply voltage (v led ). these devices are de- signed to operate with driver voltage drops (v ce ) of 0.4 v to 0.7 v with led forward voltages (v f ) of 1.2 v to 4.0 v. if higher voltages are dropped across the driver, package power dissipation will be increased significantly. to minimize package power dissipation, it is rec om - mend ed to use the lowest possible load supply voltage or to set any series dropping voltage (v drop ) as v drop = v led - v f - v ce with v drop = i o ? r drop for a single driver, or a zener diode (v z ), or a series string of diodes (approximately 0.7 v per diode) for a group of drivers. if the available voltage source will cause unacceptable dissipation and series resistors or diode(s) are undesirable, a regulator such as the sanken series sai or series si can be used to pro vide supply voltages as low as 3.3 v. for reference, typical led forward voltages are: white 3.5 ? 4.0 v blue 3.0 ? 4.0 v green 1.8 ? 2.2 v yellow 2.0 ? 2.1 v amber 1.9 ? 2.65 v red 1.6 ? 2.25 v infrared 1.2 ? 1.5 v pattern layout. this device has a common logic-ground and power-ground terminal. if ground pattern layout con tains large common-mode resistance, and the voltage between the system ground and the latch enable or clock terminals ex ceeds 2.5 v (because of switching noise), these devices may not operate correctly. dwg. ep-064 v led v drop v f v ce applications information
16-bit serial input, constant-current latched led driver A6276 12 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package a, 24-pin dip 2 0.018 1 24 a dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area for reference only (reference jedec ms-001 be) dimensions in millimeters 5.33 max 0.46 0.12 1.27 min 6.35 +0.76 ?0.25 3.30 +0.51 ?0.38 10.92 +0.38 ?0.25 30.10 +0.25 ?0.64 1.52 +0.25 ?0.38 0.38 +0.10 ?0.05 7.62 2.54 1.20 max c seating plane 0.15 max c 0.10 24x 0.65 6.10 3.00 4.32 1.65 0.45 0.65 0.25 2 1 24 3.00 4.32 (1.00) gauge plane seating plane b a a terminal #1 mark area b for reference only (reference jedec mo-153 adt) dimensions in millimeters dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown reference land pattern layout (reference ipc7351 tsop65p640x120-25m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) pcb layout reference view exposed thermal pad (bottom surface) c c 7.80 0.10 4.40 0.10 6.40 0.20 0.60 0.15 4 4 0.25 +0.05 ?0.06 0.15 +0.05 ?0.06 package a, 24-pin tssop with exposed thermal pad
16-bit serial input, constant-current latched led driver A6276 13 allegro microsystems, inc. 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com copyright ?2000-2008, allegro microsystems, inc. the products described here are manufactured under one or more u.s. patents or u.s. patents pending. allegro microsystems, inc. reserves the right to make, from time to time, such de par tures from the detail spec i fi ca tions as may be required to per- mit improvements in the per for mance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegro?s products are not to be used in life support devices or systems, if a failure of an allegro product can reasonably be expected to cause the failure of that life support device or system, or to affect the safety or effectiveness of that device or system. the in for ma tion in clud ed herein is believed to be ac cu rate and reliable. how ev er, allegro microsystems, inc. assumes n o re spon si bil i ty for its use; nor for any in fringe ment of patents or other rights of third parties which may result from its use. for the latest version of this document, visit our website: www.allegromicro.com package lw, 24-pin soicw 1.27 b reference pad layout (reference ipc soic127p1030x265-24m) all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances b 0.20 0.10 0.41 0.10 2.20 0.65 9.60 1.27 2 1 24 a 15.400.20 2.65 max 10.300.33 7.500.10 c seating plane c 0.10 24x for reference only (reference jedec ms-013 ad) dimensions exclusive of mold flash, gate burrs, and dambar protrusions exact case and lead configuration at supplier discretion within limits shown a terminal #1 mark area 0.25 gauge plane seating plane pcb layout reference view 4 4 0.27 +0.07 ?0.06 0.84 +0.44 ?0.43 2 1 24

▲Up To Search▲

Price & Availability of A6276

	To Download A6276 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .